This invention relates generally to digital computer systems and more particularly to such systems utilizing a virtual address translator (VAT) for converting a virtual address to a real address.
It is well known in the art that hierarchical memory systems provide an effective means for accommodating the large storage requirements of modern data processing systems within the constraint of economic feasibility. Basically, a hierarchical memory system utilizes a combination of relatively small, fast, and expensive main memory (real memory) for access by one or more Central Processing Units (CPU's), along with relatively large, slow, and inexpensive on-line mass storage. Because a CPU can directly access only real memory, its addressing structure must be designed to interface in terms of real addresses. The computer programs and data base elements which utilize the data processing system hardware, of course, occupy more storage capacity than is available within real memory. Therefore, at all times, some data are stored within real memory and other data are resident within mass storage. Furthermore, the composition of which data are in real memory and the addresses for these data must vary with time to permit the data processing system to perform all of its tasks within a reasonable measure of efficiency. The consequence of having no permanent real memory location or address for an individual data element means that such data element must be accessed by a CPU using a real address which varies over time.
The early art required the individual programmer to incorporate the logic within his computer programs to determine whether an individual data element is or is not in real memory, and if it is, at what real address. This requirement proved most confusing to many programmers and resulted in gross inefficiencies in the generation and utilization of computer programs. The present art uses the concept of virtual memory which permits the programmer to write computer programs without being concerned with when and where his computer program elements will reside within real memory. The concept permits him to assume a memory structure based upon virtual addressing and to refer to each datum within his computer program through the use of a virtual address. In this manner, a virtual address once assigned by the programmer does not change as the program is run in the data processing system. The data processing system is then left with the responsibility of translating the virtual address used by the computer program to reference a data element into a real address within real memory to provide the required interface between the CPU and real memory.
Various schemes have been proposed to accomplish the virtual address to real address translation. Currently, the most popular technique is to divide a computer program into segments which correspond to the types of data within the computer program (e.g., instructions, constants, variables, and program outputs). These segments are further divided into pages which are of a convenient fixed length to permit ease of transfer between directly addressable real memory and mass storage media. The term page is commonly used to refer to a page within a computer program or the amount of real memory required to store a page of a computer program. To distinguish between the two concepts when necessary, the former will be called a virtual page and the latter will be referred to as a real page. The location of a byte within a page (virtual or real) may be defined as the displacement within that page or the number of that byte position when numbering each byte position within the page. A byte within virtual memory may then be defined by providing the displacement within a virtual page, the location of that virtual page within a segment, and the computer program (or process) containing that segment. A byte within real memory may be defined by providing the displacement within a real page and the location of that real page within real memory. The virtual address to real address translation problem becomes the translating of a virtual page (within a segment, within a process) designation to a real page designation. The displacement is the same for both the virtual address and the real address.
The initial virtual address systems utilized software translation. It was found, however, that the use of special purpose hardware in the form of a Virtual Address Translator (VAT), or Directory Look Aside Table (DLAT) as is sometimes found in the art, greatly enhanced system throughput. The VAT contains internal conversion tables which provide rapid translation to real page designations of the most recently used virtual page designations. As various computer programs (or processes) utilize the CPU, new VAT entries are established replacing previous VAT entries. Prior art teaches various methods for determining when a VAT entry should be replaced with a new VAT entry. Donald B. Bennett, et al, in U.S. Pat. No. 4,096,568, teach the creation of a new VAT entry whenever a VAT miss occurs. This is a convenient method because the VAT entry is simply created simultaneously with the required software virtual address to real address translation. It was found that individual real memory accesses needed no memory protection function if the VAT was used, because the memory protection check was made at the time the VAT entry was established and subsequent translations fell within the perimeter of that protection. An additional speed enhancement was realized when no memory protection check was needed. A problem occurred, however, because of the multiple interrupt level states of CPU's. Certain memory accesses may be permitted in one interrupt level state and not another. The present art teaches that this problem is overcome by a purging (or replacing all entries) of the VAT whenever the interrupt level state is changed. This provides the desired memory protection, but it also causes a great deal of inefficiency as a CPU changes from one interrupt level state to another and back again.
The instant invention maintains the desired memory protection function while obviating the need to purge the VAT as the CPU changes from one interrupt level state to another.